This invention relates to semiconductor transistors, and specifically to insulated-gate field-effect transistors, such as metal-oxide-semiconductor (MOS) transistors.
Electronic devices ranging from discrete transistors to VLSI (Very Large Scale Integration) circuits have been improved in cost and performance in many ways over the past years. One of these ways is by reducing the size of the circuit elements used. A basic circuit element is the transistor, and in the more advanced and higher density circuits, the insulated-gate field-effect transistor (IGFET). Current technology primarily uses silicon as the semiconductor and silicon-oxide as the insulator in such transistors; the resultant transistor is thus commonly called the metal-oxide-semiconductor field-effect transistor, or MOSFET. Therefore, the smaller the MOSFET that can be fabricated, the more MOSFETs that can occupy a given surface area on a silicon slice, in turn allowing the manufacture of more complex and powerful VLSI circuits at reduced cost.
Limitations in the reduction in the size of the MOSFET often exist at the dimension of the channel length of the transistor. The channel is the area between the source and drain of a MOSFET which, in digital applications, is selectively made non-conductive and conductive to effect the desired digital operation. A well defined channel is therefore essential in fabricating a functional semiconductor device. However, as the desired channel length becomes increasingly smaller, small manufacturing errors, or small particulate contaminants, can more easily cause the channel to be permanently short-circuited, rendering the transistor and the VLSI device non-functional.
In addition, as is well known in the art, the channel length controls important electrical characteristics of the device. One of these characteristics is the value of the dependence on source-to-drain current on the gate voltage, commonly called the transconductance of the device. The switching speed of the transistor increases as the transconductance of the device increases. In order to fabricate an integrated circuit having the desired electrical behavior, the transconductance of the individual transistors within the integrated circuit must be well-controlled. This requires that the channel length of the MOS transistors in such devices must be well controlled.
It is therefore desirable that MOSFETs having very small yet controllable channel lengths be incorporated into VLSI circuit designs. Heretofore, the minimum channel lengths that have been controllable have been on the order of one micron (micrometer). Current methods, primarily photolithographic in nature, have precluded substantial manufacture of smaller transistors, since it is difficult for current equipment to print patterns of smaller than one micron, with tolerances better than 20%. If channel lengths vary by 20% within a device, or from device to device, the electrical performance of the circuits will be less than desired.
The above-referenced application describes a vertical transistor having a sub-micron channel length which can be manufactured in a highly controlled manner. This transistor is made by a process which has three diffusions to create the drain, channel and source regions, and which uses a trench cut through the diffusions so that the channel of the transistor is in a vertical direction, thereby consuming a minumum of silicon surface area and also minimizing parasitic capacitance. However, while such a transistor is easily manufactured using current techniques, the operation of the transistor is not symmetric relative to source versus drain bias. It is preferable in digital logic operations that the transistor operate the same regardless of which side of the channel is biased positive (i.e., serves as the drain in n-channel MOS) relative to the other side.
The transistor disclosed in the above-referenced application is designed for small-signal applications, since the high doping densities used in its construction, as well as the short channel length, limit the diode breakdown voltage of the source-channel p-n junction, and also cause the channel region to undergo "punch-through" at a relatively low voltage. These factors thereby limit the bias voltage which can be applied to the transistor.
It is therefore an object of this invention to provide an MOS transistor structure having a short channel length less than one (micron which is fabricated by a method allowing for a high degree of channel length control, wherein the operation of the transistor is independent of which side of the channel serves as the drain region.
It is a further object of this invention to provide a vertical MOS transistor structure having the advantages of a well-controlled channel length, minimized gate-to-drain capacitance, small utilization of silicon surface area, and which is capable of high-voltage operation.
It is a further object of this invention to provide an MOS transistor having the above advantages, and which has an improved diode breakdown voltage and an improved punch-through voltage.
Other objects and advantages of the invention will become apparent to those skilled in the art, having reference to the specification and the drawings below.